The invention relates to a method of manufacturing a semiconductor device, in which a semiconductor body is provided at a surface with a low-voltage field effect transistor and with a non-volatile memory cell in the form of a field effect transistor with a floating gate, in which method the surface is provided with a dielectric layer on which a first polycrystalline or amorphous silicon layer (further referred to as poly) is deposited which is patterned at the location of the memory cell to be formed, whereafter a first doping step is performed for forming source and drain zones of the memory cell, while, during said doping step, the region where the low-voltage transistor is formed is masked against doping by the poly layer, and in a subsequent series of steps the poly layer is patterned at the area of the low-voltage transistor, and source and drain zones of the low-voltage transistor are formed by means of a second doping step. Such a method is known from, inter alia U.S. Pat. No. 5,395,778.
For special uses, for example for microcontrollers or for chip cards, integrated circuits are nowadays required in which logic intended for the conventional data processing is combined with non-volatile memory space for the purpose of data storage. For the logic, use is preferably made of a standard CMOS process with which transistors having optimum properties can be obtained. Generally, these transistors are designed for operation at a relatively low voltage, i.e. at a voltage of less than, for example 5 V. The memory consists of memory cells each comprising a transistor with a floating gate. Usually, a control gate, which is electrically separated from the floating gate by means of an intermediate insulating layer, is arranged above this floating gate. Written information is represented by the charge state of the floating gate which determines the threshold voltage of the transistor. The information can be read by determining the conduction of current through the transistor at a given voltage across the control gate.
Said U.S. Pat. No. 5,395,778 describes a method in which, with a minimal number of extra process steps, a CMOS circuit made in a standard CMOS process is combined with a non-volatile memory in a common silicon body. Since the manufacture of such a non-volatile memory is not compatible with a standard CMOS process, said U.S. Pat. No. 5,395,778 proposes a method in which first a series of essential steps is performed for manufacturing the memory, such as the definition of the floating gate from a polycrystalline silicon layer (poly silicon), a doping step for the source/drain and an oxidation step for oxidizing the side walls of the floating gate. During these steps, the active regions of the semiconductor body where the logic is provided are entirely masked by the poly layer. When the essential steps of providing the memory have been performed, the process can be continued with the standard CMOS process for the logic.
In certain types of non-volatile memories, it is desirable to use voltages which are higher than 5 V, for example a voltage of 9-20 V. This situation occurs, for example in memories of the EEPROM type in which use is made of the Fowler-Nordheim tunnel mechanism during writing and/or erasing. To supply such relatively high voltages, the peripheral electronics of the memory require transistors which can cope with these high voltages and must therefore have a breakdown voltage of approximately 14 V. In addition to these transistors, here referred to as high-voltage transistors, each cell in an EEPROM is usually provided with an access transistor which isolates the memory cell electrically from other memory cells and connects the floating gate transistor to a bit line, and which should also be able to cope with said high voltage. This transistor is usually of the same conductivity type as the memory transistor.